The zero-crossing phase-lock loop: results from discrete dynamical theory

Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. Howev...

Introduction To Phase-Lock Loop System Modeling

Phase-lock loops (PLLs) have been one of the basic building blocks in modern electronic systems. They have been widely used in communications, multimedia and many other applications. The theory and mathematical models used to describe PLLs come in two types: linear and non-linear. Non-linear theory is often complicated and difficult to deal with in real-world designs. Analog PLLs have been well...

Switched Reference Phase Lock Loop (srpll)*

The Brookhaven National Laboratory Relativistic Heavy Ion Collider (RHIC) has two beam synchronous event links (BSL), one for each ring, which use the 28 MHz ring low level rf to distribute event codes synchronously with a precise phase relationship to the beam. During a cogging reset just before injection, the low level rf sine wave is interrupted which causes the BSL receivers to lose lock. L...

Delay Lock Loop Assisted Phase Lock Loop for GNSS Signal Tracking

—For positioning with Global Navigation Satellite System (GNSS) in urban canyon area, besides the weak signal power, the satellite signal may also be frequently sheltered and no power can be received. It is a great challenge for the GNSS receiver to keep positioning continuously. If the tracking loop in GNSS receivers can recover locking the signal soon after the signal appears again, it will ...

Tunneling in the condensed phase : barrier crossing and dynamical control